by
Intel's "PC On-Chip" includes dual Atom processor cores, and a complete RF WiFi transceiver... Check out !
In the
Q&A session following the presentation, Lakdawala said that the
digital portion of the WiFi modem was implemented in software off-chip,
separate from the RF, implying that the design presented is not yet a
complete standalone single-chip solution. In response to a discrepancy
between the presentation, which decribed the WiFi transceiver as
802.11b/g/n, whereas the text of the paper in the ISSCC Digest describes
only 802.11b/g, the author said that a higher Signal-to-Noise would
have been required for the 802.11n, but the architecture supports it.
Intel presented four of the eight papers in the Processor session at the International Solid State Circuits Conference (ISSCC) on Monday, February 20. In paper 3.4, Intel research scientist Hasnain Lakdawala described a "32nm x86 OS-Compliant PC On-Chip with Dual-Core Atom® Processor and RF WiFi Transceiver".
The integration of a complete 2.4GHz WiFi transceiver along with
peripheral I/O blocks and dual Atom processor cores is targeted by Intel
at embedded PC applications, such as wireless industrial controllers.
Lakdawala
started his presentation by pointing out three key requirements for such
a project: a fabrication process that is compatible with both analog/RF
and digital functions, an IP block integration methodology, and
scalable analog and RF components. The 32nm Intel CMOS process provides
three different transistors: logic transistors (in both standard and
high-performance models), low power transistors with lower leakage, and
high-voltage I/O devices. Quality passive components, especially
inductors, are also required. Intel's process includes an RF optimized
metal stack, and a high-resistivity substrate to minimize eddy current
losses. Lakdawala reported two different results for on-chip inductors.
Small inductors, on the order of 0.5nH, achieved Qmax of ~25. Larger,
5nH inductors, achieved a Qmax of >15 for 5nH.
Intel
designed a new proprietary interconnect fabric for the "PC on a chip",
the Intel On-chip System Fabric (IOSF), which connects the various
semiconductor intellectual property (SIP) blocks: Universal asynchronous
receiver/transmitter (UART), General Purpose Input-Output (GPIO),
Secure Digital Input-Output (SDIO), Peripheral Component Interconnect
Express (PCIe), Real-time Interrupt Controller (RTIC), and Double
Data-Rate RAM Interface (DDR I/F). The IOSF also provides test, debug
and validation capability, with visibility to individual IP blocks and
an on-chip logic analyzer.
The Atom
processor in the PC SoC was scaled from a 45nm core, said Lakdawala, and
supports 2-way simultaneous multi-threading.He said that the core is
"CAN-ready" (Controller Area Network), which eases testing. To minimize
power, the SoC supports Burst Mode to increase the clock speed when
higher performance is required, and both the core and the L2 cache
employ power gating. The chip also uses the ATOM-style C5 power state.
For industrial applications, digital temperature sensors are provided
for each core. The architecture supports both Windows and Linux
operating systems.
A unique
feature of the PC On-Chip is the Spread Spectrum Clock generator (SSC).
All of the system clocks are derived from the 2.5GHz required for the
WiFi transceiver. The SSC is used to spread the frequencies of the
clocks for the CPU, DDR3, SATA and PCIe blocks by up to 0.5%, in order
to reduce the energy of clock noise that is coupled to the SoC
substrate, to improve isolation of the RF blocks.
The WiFi
transceiver includes a Low-Noise Amplifier (LNA), Power Amplifier (PA),
and two transmit/receive switches for simultaneous operation. Lakdawala
said that having the PA on-chip tends to pull the Phased-Locked-Loop
(PLL), which was prevented by operating at 4X the WiFi channel
frequency. A separate on-chip processor and dedicated data path provides
a test and calibration engine for the WiFi transceiver. The only
remaining off-chip RF component is the balun used to convert the 50-ohm
differential output to a single-ended connection to the antenna.
